1. Field of the Invention
This invention relates to a structure for and method for fabrication of insulated-gate field-effect (IGFET) semiconductor devices using polysilicon gates. In particular, this invention relates to a structure and method for providing a self-aligned contact hole through overlying passivation layers to an active source or drain region in an IGFET device that substantially reduces the spacing between the gate and source and drain contact holes.
2. Description of the Prior Art
An insulated-gate field-effect semiconductor device, hereinafter sometimes referred to as an IGFET device, comprises a substrate of semiconductor material of one conductivity type having a principal surface. Spaced regions of opposite conductivity type, referred to as the source and the drain, are located in the substrate and form PN junctions with the substrate, each junction extending to have an edge at the principal surface. A layer of passivation material overlies the principal surface to protect the surface edge of the PN junctions from contamination. Located over a portion of the passivation layer between the underlying source and drain is a strip of conductive material, referred to as the gate. Voltage potentials applied to the gate control the electrical field in the space between the source and drain, referred to as the channel, and consequently, the flow of electrons or holes between the source and drain.
For many applications, it is desirable to use polysilicon semiconductor material for the gate.
Electrical contact to the source and drain is made by forming a hole through the overlying passivation layer down to the principal surface of the substrate to expose a portion of the source and drain. Conductive metal is deposited in the hole over the source or drain to provide electrical contact thereto.
Depending upon how closely one can align the contact hole to a desired location, usually within 2 or 3 microns, it is desirable to leave a spaced separation of 4 to 5 microns between an edge of the polysilicon gate and an edge of the source or drain contact hole. This separation helps to ensure that the contact hole does not overlap the gate, which would cause an electrical short to occur between the gate and metal in the source or drain contact hole.
With the increasing trend in the semiconductor field toward the development of large-scale integration devices and semiconductor memories, in which many active elements are fabricated close together on a single piece of semiconductor material, often referred to as "chip," it is desirable to fabricate as many elements as possible on the chip.
The amount of surface area of a chip needed per active element often determines how many elements can be made in the chip. Thus, it is desirable to reduce the amount of surface area needed per active element. With such high-density devices, the requirement of allowing a space of 4 to 5 microns between the gate and the source and drain contact holes of an IGFET device means that the potential density of a device is substantially reduced. Thus, there is a need to reduce the separation between the gate and source or drain contact. hole while preventing electrical shorts between the gate and the metal located in the source or drain contact hole.